The present disclosure relates generally to integrated circuit (IC) design, and more particularly to an improved design for handling data abort conditions.
In a processor system, data and instruction values are read to and written from a memory subsystem. The memory subsystem may issue an abort instruction to the processor upon the occurrence of a memory access rule violation or other access rule violation. When an abort condition occurs, the processor must properly flush any instructions that might have been pipelined following the aborted instruction.
In addition, the memory subsystem negates any controls that would change processor status registers. Typically, a data abort recovery process is performed to detect the abort condition in the memory access clock cycle. Usually, the logic intercepts the status register update controls. When the current memory access instruction is aborted and a state changing instruction is the next pipelined instruction, the interception of the status register update controls ensures that the prior register state can be maintained. It is, however, disadvantageous to add additional circuit component or logic in the abort condition sampling path. Even if additional logic is allowed to be implemented, since the memory subsystem requires certain time to determine an abort condition, it is desired, from the perspective of system timing, for the processor to sample an abort condition indicator as late as possible in a memory access clock cycle so as to avoid creating critical timing paths in the processor and memory subsystem.
What is needed is an improved method and system for maintaining the proper register status state while validating the abort condition as late as feasible in the memory access clock cycle.